{"id":21568,"date":"2026-10-15T12:13:59","date_gmt":"2026-10-15T12:13:59","guid":{"rendered":"https:\/\/news.theck1.no\/?p=21568"},"modified":"2026-10-15T12:13:59","modified_gmt":"2026-10-15T12:13:59","slug":"sk-hynix-to-place-custom-tiny-cpu-cores-in-its-ssd-controllers-to-ease-arm-load-as-drive-speeds-rocket","status":"publish","type":"post","link":"https:\/\/news.theck1.no\/?p=21568","title":{"rendered":"SK hynix to place custom tiny CPU cores in its SSD controllers to ease Arm load as drive speeds rocket"},"content":{"rendered":"

AI-rewritten:<\/strong> This is a summary of an article from Tom’s Hardware, rewritten by AI (Qwen, running locally) to make it easier to read. The facts come from the original article – read it for the full story.<\/p>\n

Tom’s Hardware • Shane Downing • October 14, 2026<\/strong><\/div>\n\n

SK hynix plans to introduce custom tiny CPU cores called H-TPUs into its SSD controllers to reduce reliance on power-hungry general-purpose processors. These specialized units handle repetitive input\/output tasks using a four-stage pipeline that processes commands sequentially. According to SK hynix, these new cores consume only about 2.5% of the power and occupy roughly 4% of the area compared to standard CPU cores. The traditional Arm CPU will continue managing overall system operations, error recovery, and storage policies, while the H-TPUs focus on specific duties like metadata management and buffer control.<\/p>\n

<\/p>\n

Company executive Koo In-jae explained at the ISOCC 2026 conference that current SSD controller CPUs are reaching limits regarding power and space as PCIe bandwidth doubles with every generation. He noted that competitors often solve this by adding more cores, such as Marvell’s use of multiple Cortex-R8 and Cortex-M7 clusters. SK hynix avoids this approach by designing smaller, programmable H-TPUs supported by dedicated compilers. The company has filed patents describing a control plane where data passes through four stages\u2014host ingestion, cache, mapping, and NAND storage\u2014using many small processors to configure the pipeline for each operation.<\/p>\n

SK hynix intends to deploy these cores across its portfolio, including next-gen enterprise SSD controllers and upcoming high-bandwidth flash (HBF) products due next year. The H-TPU design is being tested in collaboration with Nvidia on a project called Storage Next, which targets large NAND access sizes for AI inference workloads. While the technology has not yet been proven in an actual enterprise product, SK hynix aims to use it to handle high IOPS demands without the power penalty of scaling up traditional CPU cores.<\/p>\n

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Source:<\/strong> Tom’s Hardware • Shane Downing • October 14, 2026<\/p>\n

Read the original article at Tom’s Hardware →<\/a><\/p>\n<\/div>\n","protected":false},"excerpt":{"rendered":"

AI-rewritten: This is a summary of an article from Tom’s Hardware, rewritten by AI (Qwen, running locally) to make it easier to read. The facts come from the original article – read it for the full story. Tom’s Hardware • Shane Downing • October 14, 2026 SK hynix plans to introduce custom tiny CPU cores<\/p>\n

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